(a) Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having a package structure in which a chip, such as a semiconductor element or electronic component, is mounted within a wiring board. In the following description, for convenience, a semiconductor device in which a chip is mounted within a wiring board is also referred to as a “chip-embedded package.”
(b) Description of the Related Art
In recent years, for printed wiring boards, weight reduction is required, and finer and denser wiring is required in order to mount a ball grid array (BGA), a pin grid array (PGA), a chip-sized package (CSP), or the like, which have been miniaturized and come to have a large number of pins. However, since conventional printed wiring boards have needed large areas for the formation of via holes, flexibility in design has been limited, and thus finer wiring has been difficult to realize. In view of this background, the commercialization of printed wiring boards (build-up multilayer wiring boards) using a build-up process has been recently advanced. As for the build-up multilayer wiring boards, various types can be fabricated depending on a combination of the material for an interlayer insulating layer and the via hole formation process. In a basic process thereof, conductor layers are stacked by sequentially repeating the formation of an insulating layer, the formation of via holes for interlayer connection in the insulating layer, and the formation of a conductor layer (patterned interconnections, pads, and the like) including the insides of the via holes. In a multilayer wiring board obtained using such a build-up process, even a semiconductor element (chip) having an advanced integration degree and the like can be mounted thereon.
On the other hand, as a technique of increasing the integration degree and versatility of a semiconductor device, a package structure has been proposed which is intended to form a required circuit block by incorporating a semiconductor element (chip) in a board or stacking semiconductor elements (chips) in a board. In this package structure, since the chip (or chips) is embedded in the board, via holes for vertical interlayer connection cannot be formed in a region corresponding to a mount area for the chip. Accordingly, via holes for interlayer connection are formed in a region around the region corresponding to the mount area for the chip.
Further, in an existing build-up multilayer wiring board into which a chip is incorporated, via holes for interlayer connection are formed on through holes formed in a core substrate. Namely, as in the case of the via holes, the through holes are also formed in a region around the region corresponding to the mount area for the embedded chip. FIG. 11 shows one example thereof. In this drawing, reference numeral 1 denotes an insulating core substrate; reference numeral 2 denotes a plated layer of metal (e.g. copper (Cu)) which is formed on the inner wall and an end portion of a through hole TH formed in the core substrate 1; reference numeral 3 denotes resin (e.g. epoxy resin) as an insulator filled inside the plated layer 2 in the through hole TH; reference numeral 4 denotes a conductor (e.g. Cu) layer thickly formed (approximately 50 μm) on the through hole TH; reference numeral 5 denotes a build-up resin as an interlayer insulating layer; and reference numeral 6 denotes a wiring layer formed by filling the inside of a via hole VH formed on the conductor layer 4 on the through hole TH. The wiring layer 6 is formed in a required pattern shape and connected to electrodes of an embedded chip (approximately 50 μm in thickness). The purpose of thickly forming the conductor layer 4 is to match the height of the surface thereof to that of the mounted chip.
Technologies relating to the above-described conventional technology include, for example, as described in Japanese unexamined Patent Publication (JPP) 2001-177045, a semiconductor device in which a wiring pattern is formed on a core substrate with an insulating layer interposed therebetween, and in which a semiconductor element having a thickness smaller than that of the insulating layer is electrically connected to the wiring pattern by flip-chip bonding and is mounted in an internal portion where the wiring pattern is formed.
In the conventional chip-embedded package, as described above, as illustrated in FIG. 11, the through hole TH of the core substrate is formed in a region around the embedded chip. Further, the via hole VH is formed on the through hole TH (filled resin 3) with the thickly-formed conductor layer 4 interposed therebetween. In this case, the conductor (part of the wiring layer 6) to be filled in the via hole VH is not formed in the same step, as the conductor layer 4 is, to be integrated therewith, but is formed on the conductor layer 4 after the formation of the conductor layer 4, the deposition of the build-up resin 5, and the formation of the via hole VH.
Accordingly, where a temperature cycling test (e.g. test in which the following cycle is repeated several times: the environmental temperature for the package is raised to +125° C. and maintained for a certain period of time, then rapidly lowered to −125° C. and maintained for a certain period of time, and then rapidly raised to +125° C. and maintained for a certain period of time) is performed on the above-described structure, there is a possibility in that, due to thermal stress caused by temperature changes, cracks will appear at the connection interface between the conductor layer 4 and the conductor (6) in the via hole VH which is in contact with the conductor layer 4 (see FIG. 11). This is not so serious if a portion in which cracks appear is merely part of the connection interface. However, in the case where cracks spread all over the connection interface (i.e. rupture occurs at the connection interface), there arises a disadvantage in that the electrical connection between the conductor layer 4 and the wiring layer 6 is not secured. This results in a deterioration in the reliability of the semiconductor device as a final product.
Moreover, there has been the following problem: during the temperature cycling test, there occurs a phenomenon (so-called “pumping”) in which the resin 3 in the through hole TH expands and contracts by repeating thermal expansion and thermal contraction, and the pumping acts as a trigger and makes the above-described cracks more easy to appear. Further, such pumping can occur not only in the resin 3 in the through hole TH, but also in the build-up resin 5. Accordingly, there has also been the following problem: depending on the degree of the expansion or contraction of resin caused by pumping, the wiring layer 6 formed on the build-up resin undulates, and, in some cases, cracks in wiring are caused.